- queue with gating
- система массового обслуживания с управлением пропусканием
The English-Russian dictionary on reliability and quality control. 2015.
queue with gating
Смотреть что такое "queue with gating" в других словарях:
Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… … Wikipedia
Out-of-order execution — In computer engineering, out of order execution (OoOE or OOE) is a paradigm used in most high performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay. In this paradigm, a… … Wikipedia
Xtensa — is a 32 bit microprocessor core designed by Tensilica.Tensilica describes it as a configurable, extensible and synthesizable processor core ... the first microprocessor architecture designed specifically to address embedded System On Chip (SOC)… … Wikipedia
CPU cache — Cache memory redirects here. For the general use, see cache. A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the… … Wikipedia
Memory management unit — This 68451 MMU could be used with the Motorola 68010 A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware component responsible for handling accesses to memory requested by the CPU. Its… … Wikipedia
AMD K10 — The AMD K10 is AMD s latest microprocessor architecture. Though there were once reports that the K10 had been cancelled [http://www.theinquirer.net/?article=27421 AMD s K10 is delayed or dead] , The Inquirer] , the first third generation Opteron… … Wikipedia
Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… … Wikipedia
